The x86 architecture defines that if an x86 Shift instruction (SHR or SHL, referred to generically as SHF) is by an amount of zero, the EFLAGS are unchanged; otherwise, the EFLAGS bits are updated to reflect the result of the shift operation. This poses a problem when determining dependencies of a Condition Code (CC) instruction (i.e., a reader of EFLAGS, such as Jcc/Setcc/Movcc) that follows an x86 SHF instruction. The following sequence exemplifies the problem:
ADD EAX, EBX;writes EFLAGSSHR EDX, CL;writes EFLAGS, only if shift amount(in CL) is non-zeroJZ <target>;uses EFLAGS
If the value of CL is zero, then the JZ will be dependent upon the ADD; whereas, if the value of CL is non-zero, then the JZ will be dependent upon the SHR. Unfortunately, at the time the register alias table (RAT) determines the dependencies, it does not have any way of knowing whether the value of CL is zero or non-zero. Therefore, in older designs of a microprocessor:                a) the RAT makes the JZ dependent upon the SHR, and        b) the RAT makes the SHR dependent upon the ADD (i.e., upon the most recent older EFLAGS-modifying instruction).        
This causes the SHR to receive the EFLAGS value from the ADD, which it needs because if the value in CL is zero, the SHR must supply to the JZ the EFLAGS value received from the ADD, since according to the x86 architecture definition the SHR does not modify EFLAGS if CL is zero. The present inventors have observed that the extra dependency of a SHF upon the most recent older EFLAGS-modifying instruction, which is only needed for the shift-by-zero case, is causing SHFs to be issued to the execution units later than necessary and hurting performance. (It is noted that the problem only occurs for SHFs of the form “SHF Reg, Reg”, i.e., the shift amount is supplied from a register that is populated by an older instruction; whereas, for SHFs of the form “SHF Reg, Imm”, the RAT can know early on from the Imm field whether the shift amount is zero and can set dependencies correctly at that time.)